• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a circuit comprising, in series between a first terminal (508) and a second terminal (509) for applying a supply voltage (VCC): a first branch comprising a first transistor (501) and a first current source (506); a second branch comprising a resistive element (503), a second transistor (502) mounted in a mirror of the first transistor and a second current source (507), said resistive element conditioning a detection threshold of a variation of the voltage of food.
    公开号:FR3042876A1
    申请号:FR1560259
    申请日:2015-10-27
    公开日:2017-04-28
    发明作者:Bruno Leduc；Pascal Bernon；Stephane Clin
    申请人:STMicroelectronics Alps SAS；
    IPC主号:
    专利说明:

    DETECTION OF DISTURBANCES OF A POWER SUPPLY
    Field
    The present application relates generally to electronic circuits and more particularly to the detection of deliberate or accidental disturbances of the normal operation of a circuit.
    A particular application is the detection of an attempt to hack a secure electronic system such as the payment means commonly called smart cards.
    Statement of Prior Art
    Secure smart cards, because of the information they contain, arouse the envy of hackers who have developed accordingly many ways to access the content of cards. One of the known methods is the injection of faults.
    There is therefore a need to improve the robustness of the systems against attempts to disrupt their operation. summary
    One embodiment proposes to improve the existing circuits detecting deliberate disturbances of a supply voltage.
    One embodiment proposes to reduce the detection threshold of power disturbances.
    One embodiment proposes making the detection threshold independent of technological manufacturing variations.
    One embodiment proposes to overcome temperature variations.
    One embodiment proposes making the detection threshold programmable during circuit fabrication or in use.
    Thus, an embodiment provides a circuit comprising, in series between a first terminal and a second terminal for applying a supply voltage: a first branch comprising a first transistor and a first current source; a second branch comprising a resistive element, a second transistor mounted in a mirror of the first transistor and a second current source, said resistive element conditioning a detection threshold of a variation of the supply voltage.
    According to one embodiment, the circuit comprises a low-pass filter connected to the gates of the transistors mounted in current mirror.
    According to one embodiment, a low-pass filter couples the first power supply terminal and the resistive element.
    According to one embodiment, said transistors are MOS transistors.
    According to one embodiment, said transistors are bipolar transistors.
    According to one embodiment, said current sources are made with transistors.
    According to one embodiment, the ratio of the dimensions of the transistors constituting the current mirror and the ratio of the transistors constituting the current sources are different from 1.
    According to one embodiment, the resistance of the resistive element is programmable.
    According to one embodiment, the current sources are obtained from a voltage reference independent of the temperature and a resistor of the same type as the resistive element conditioning the detection threshold.
    An embodiment provides a device comprising: a power regulator; a function powered by said regulator; and a circuit as above.
    According to one embodiment, said circuit is powered by said regulator.
    According to one embodiment, said circuit is fed upstream of said regulator.
    Brief description of the drawings
    These and other features and advantages will be set forth in detail in the following description of particular embodiments made without implied limitation in relation to the appended figures in which: FIG. 1 represents a schematic and simplified view of a smart card and reader; Figure 2 shows a schematic view of different possible states of a smart card; FIG. 3 represents an example of the shape of the supply voltage of a circuit and illustrates an injection attack of a supply disturbance; FIG. 4 represents an exemplary circuit detecting a disturbance of the supply voltage; FIG. 5 represents an embodiment of a positive disturbance detection circuit; Figs. 6A and 6B are timing diagrams illustrating a power disturbance attack; Fig. 7 shows an embodiment of a negative disturbance detection circuit; FIG. 8 represents an embodiment of a device integrating a power disturbance detector; and FIG. 9 represents another embodiment of a device incorporating a power disturbance detector.
    detailed description
    The same elements have been designated with the same references in the various figures. For the sake of clarity, only the elements that are useful for understanding the described embodiments have been shown and are detailed. In particular, the application functions of the protected circuit have not been detailed, the described embodiments being compatible with the usual applications.
    Unless otherwise specified, the terms "approximately", "substantially", and "of the order of" mean within 10%, preferably within 5%.
    Figure 1 shows, schematically and simplified, a smart card 101 (IC CARD) and a reader 102 (READER).
    A smart card generally comprises at least one memory element 103 (MEMORY) in which the information is stored, an element fulfilling an interface function with the outside world 104, called an access control (ACCESS CONTROL), and an element feeding card 105 (POWER). The smart card may include additional elements.
    Figure 2 shows a schematic view of different possible states of a smart card. In order to access the information contained in the card 101 (FIG. 1), the card 101 must be presented to a card reader 102. The smart card then goes through an authentication process 201 (AUTHENTICATION CHECK) during which the card reader 104 access verifies that a key provided by the reader during the communication protocol is in accordance with the key allowing access to the memory. If the condition is fulfilled, then access to the secure card information is permitted and the card goes into an ACCESS ALLOWS SHARE / CHANGE SECURE INFORMATION state. If the condition is not met, access to secure information is not allowed. Note that the described process is simplified and that other access control processes may exist as well.
    In normal operating mode, a smart card is designed to go through specific states to give or not permission to access the data stored in its memory 103. A known method of injecting faults consists in causing the setting in indeterminate state 203 of the smart card (UNDEFINED STATE), allowing an attacker to access secure information without going through the authentication phase.
    FIG. 3 represents an example of the shape of the supply voltage VCC of a circuit and illustrates an injection attack of a disturbance of the supply. To put a circuit in the indeterminate state 203 (Figure 2), it imposes a disturbance outside the range of supply voltage (UPPER ACCEPTABLE VCC / LOWER ACCEPTABLE VCC) for which the circuit is designed.
    For the attack to be effective, the disturbance must be long enough to have an effect and short enough not to turn off the circuit or damage it. Likewise, the amplitude of the disturbance is chosen so as to disturb the circuit without turning it off or damaging it.
    There is therefore a need to counter attempts to disrupt supply voltages of devices containing secure information.
    According to one embodiment, an attempt is made to disturb the power supply of the circuit contained in the smart card. The information is then provided to a system that applies countermeasures, for example disabling the card, destroying data, etc.
    FIG. 4 represents an exemplary circuit detecting a disturbance of the supply voltage. The circuit includes a resistor 402 and a capacitor 403, in series between a power supply potential terminal (VCC) 405 and a ground connection terminal 406 (GND), and a PMOS transistor 401. The gate of the transistor 401 is coupled to the node common to the resistor 402 and the capacitor 403, its source is coupled to the supply terminal 405 and its drain is coupled to a current source 404 whose other end is connected. to the mass. The output 407 (OUT) of the circuit is taken at the drain of the transistor. The circuitry for converting the current level crossing the transistor into a logic equivalent of value 0 or 1 according to whether the current is zero or non-zero is not represented.
    When there is no supply disturbance, the PMOS transistor 401 is blocked, the current flowing through it is zero, the output OUT is therefore at a logic level 0.
    When a supply disturbance occurs, the VCC potential (405) increases, which increases the gate-source voltage VGS of the transistor. If this voltage VGS is greater than the threshold voltage VT of the transistor, then it switches in conduction and is crossed by a current. As a result, the OUT output changes state. Thus, a power supply disturbance was detected.
    A disadvantage of this circuit is that the amplitude of the disturbance must be greater than the voltage VT of the transistor to be detected. In other words, the detection threshold of the supply disturbance is greater than the voltage VT.
    To minimize electricity consumption and gain integration, the trend is to move towards technologies with increasingly lower supply voltages.
    We have thus gone from supply voltages of the order of 5V to voltages of approximately 1.5V, while at the same time the threshold voltage values VT have slightly decreased and are still of the order of 600-700 mV. As a result, much smaller power supply variations, lower than the threshold voltage levels VT, make this type of detection system inoperative. Indeed if we design circuits allowing a variation of the supply voltage of 10% around a nominal value, from 5V to 1.5 V, the supply voltage varies from 500 mV to 150 mV . It can therefore be seen that it is difficult to detect an attempt to disturb the power supply based on a detection system based on threshold voltages VT of the order of 700mV. Advanced technologies offer transistors with low threshold voltage VT, but they are expensive and not compatible with the economic criteria of the smart card market.
    Another disadvantage is that the threshold voltages of the transistors vary with the technological dispersions of manufacture. Thus, the threshold of detection of disturbance also depends on the dispersions, which induces that within a population of circuits manufactured there are strong variations of detection threshold.
    Another disadvantage is that this type of circuit does not make it possible to adjust the detection threshold of power disturbances.
    Another disadvantage is that this circuit does not detect power supply disturbances below the minimum level of supply voltage.
    Another disadvantage is that the detection threshold varies with temperature.
    There is therefore a need for a circuit detecting a positive or negative power supply disturbance (above the maximum permissible voltage or below the minimum tolerated voltage), independently of the thresholds of MOS transistors, whose detection threshold is independent of manufacturing variations and temperature variations, and whose threshold is adjustable during circuit production or in the final application.
    Fig. 5 shows an embodiment of a positive disturbance detection circuit.
    The circuit comprises a MOS transistor 502 mounted in mirror of a MOS transistor 501, the two transistors having their drains respectively coupled to two current sources 506 and 507. The other terminals of the current sources are coupled to a connection terminal 509. the mass (GND). The circuit further comprises a capacitor 505, one end of which is coupled to the gate of the transistors 501 and 502 and the other end of which is connected to the terminal 509, and a variable resistor 503 of which one terminal is connected to the source of the transistor 502 and whose other end is coupled to the terminal 508 for applying a supply potential (VCC). The source of the transistor 501 is coupled to the terminal 508. The output OUT of the circuit is taken at the drain of the transistor 502.
    FIGS. 6A and 6B are timing diagrams respectively illustrating an example of the shape of the supply voltage V508 of the circuit and the corresponding current Iout passing through the transistor 502 of the circuit of FIG. 5. FIG. 6A illustrates an example in which a disturbance is applied between two instants tA and tB. FIG. 6B illustrates the current Iout, part of which comes from a bias current denoted 10 and another part of which comes from the current induced by the disturbance.
    The electrical assembly of FIG. 5 imposes: VGS2 = VGS1-R2x1 (eq1), with: VGS1 representing the voltage between gate G1 and source S1 of transistor 501; VGS2 representing the voltage between gate G2 and source S2 source of transistor 502; R2: representing the value of the resistor 503.
    One can also write: I = 10 + iac; iac representing the disturbance current.
    When there is no supply disturbance (iac = 0), the transistor 502 is biased by the current 10 (FIG. 6B) which is not zero thanks to the transistor 501 mounted in a diode, it is therefore in the idle mode. It follows that any potential variation of the node 508 will be instantaneously seen by the transistor since the transistor is already biased to be off contrary to what happens in the case of FIG. 4.
    Indeed, by equation 1, if the potential of the node VCC rises, the source of the transistor 502 follows the voltage of the node 508.
    In the case where the resistor 503 is zero, since the transistor is already in the quiescent state, there is immediately a current superimposed on the quiescent current, and the state of the output OUT changes, which can be interpreted as a transition from a logical level 0 to a logical level 1.
    We now have an independent detection of the voltage VT of the MOS transistor 502 and the detection threshold is of the order of a few millivolts instead of being of the order of the threshold VT of the MOS transistor.
    In the case where the resistor 503 is non-zero, if the potential VCC increases, the voltage VGS1 increases in absolute value because the potential of the source of the transistor 501 rises with the voltage VCC. At the same time, the potential of the source of the transistor 502 rises, and the voltage VGS2 in absolute value also.
    As long as the amplitude of the disturbance is strictly less than R2 x I, the level of the voltage VGS2 is not sufficient for the transistor 502 to induce an additional current to the bias current. The OUT output remains in its idle state.
    When the amplitude of the disturbance is greater than or equal to R2 × I, the transistor 502 generates an additional current superimposed on the bias current, and the output OUT changes value which can be interpreted as a logical change of state.
    A positive power disturbance detector has therefore been realized, the detection threshold of which is independent of the threshold VT of the transistors and whose value is adjustable by means of the resistor 503 and the quiescent current flowing through the transistor 502.
    Transistor 501 is equivalent, as a first approximation, to a small signal model, in contrast to its conductance gm, ie to a resistance of value R1. Thus, the resistance and capacitance 505 of value C1 form a low-pass filter. By adjusting the value of this low-pass filter it is therefore possible to define the maximum frequency of the power disturbances detectable by the circuit.
    When the potential of the node 508 rises, the potentials of the source S1 and the gate G1 also rise.
    If the frequency of the disturbance is less than 1 / (2nRlCl), because of the action of the low-pass filter, the potential of the gate G2 rises at the same time as that of the gate G1. Since the potential of the source S2 follows the potential of the node 508, the voltage VGS2 does not change because its potentials vary approximately of the same amplitude.
    On the other hand, if the frequency of the disturbance is greater than 1 / (2nRlCl), then the variation of the potential of the gate G2 is attenuated because of the filter with respect to the variation of the potential of the gate G1. Thus, the potential of the gate G2 does not rise as quickly as that of the source S2 which follows the potential of the node 508, which induces a change in the voltage VGS2.
    The capacitor 505, between the gate of the transistors 501 and 502 and the mass 509, makes it possible to adjust the frequency of the disturbances detected.
    Another embodiment which can be combined with or not with the preceding one consists in making the value of the programmable detection threshold by means of a variable resistor, via a network of switched resistors or any other equivalent means.
    In the embodiment described, the transistors 501 and 502 have a ratio of dimension W / L (W and L being respectively the width and the length of the gate of the transistors) equal and the values of the currents passing through the current sources 506 and 507 are equal.
    One embodiment consists of designing the current sources by means of MOS transistors, and configuring the circuit so as to have a W / L dimension ratio for the transistor 502 and kx W / L for the transistor 501 with k different from 1 Likewise, a W / L ratio for the current source 506 and kx W / L for the current source 507 is provided. This configuration has the advantage of minimizing the consumption in the branch of the transistor 501 and the source. 506. Other report configurations may exist.
    Another embodiment consists in using bipolar transistors instead of MOS transistors. Similarly, it will be possible to play on the current ratios by having different emitter surface ratios between the two branches.
    Another embodiment is to design the current sources 506 and 507 so that the reference current from which they are derived, is obtained by the ratio between a band-free voltage and a resistor of the same type as the resistor 503. An embodiment is thus obtained in which the detection threshold of the supply disturbances is independent of the temperature variations.
    FIG. 7 represents an embodiment of a negative disturbance detection circuit.
    The circuit includes a resistor 704 and a capacitor 705 in series between a power supply terminal (VCC) 708 and a ground connection terminal 709 (GND). The circuit further comprises a MOS transistor 702 mounted in mirror with a MOS transistor 701, the two transistors having their drains respectively coupled to two current sources 706 and 707. The other terminals of the current sources are coupled to the ground 709. The source of the transistor 701 is coupled to the terminal 708 for applying a supply potential, the source of the transistor 702 is coupled to a terminal of a resistor 703, the other terminal of this resistor being coupled to the common node to the resistor 704 and the capacitor 705. The output OUT of the circuit is taken at the drain of the transistor 702.
    The operation of this embodiment is similar to that of Figure 5.
    A supply disturbance detection is carried out whose threshold is defined by the value R4 of the resistor 703 and by the quiescent current flowing through the transistor 702.
    The low-pass filter is produced by the resistor 704 of value R3 and by the capacity 705 of value C3.
    We call: VGS3, the voltage between the gate G3 and the source S3 of the transistor 701 VGS4, the voltage between the gate G4 and the source S4 of the transistor 702.
    The difference with respect to the embodiment of FIG. 5 lies in the fact that when a negative perturbation appears, it is now the grid of the current mirror which follows the disturbance and not the then common source.
    Indeed, when the potential of node 708 decreases, this reduction is propagated on the gate of transistor 701 and therefore on that of transistor 702.
    On the source side of the transistor 701, if the frequency of the disturbance is less than 1 / (2nR3C3), the decrease of the potential of the node 708 is propagated on the source of the transistor 702, but this does not induce a change in the voltage VGS4 because the potentials of the gate G4 and the source S4 of the transistor 702 have varied in the same order of magnitude.
    On the other hand, if the frequency of the disturbance is greater than 1 / (2nR3C3), then the reduction of the potential of the node 708 is propagated on the source of the transistor 702 but with a level shift due to the action of the pass filter. low. From the moment when the amplitude of the disturbance exceeds the product of the value of the resistor 703 and the quiescent current passing through the transistor 702, the voltage VGS4 increases in absolute value. An additional current then appears in the transistor 702, which induces the change of the state of the output OUT, which can be interpreted as a logical change of state.
    A circuit has thus been realized which detects so-called negative supply disturbances.
    The variants described for the embodiment of FIG. 5 can be adapted to the embodiment of FIG. 7.
    Another embodiment consists in combining the circuits for detecting positive and negative power disturbances in the same circuit.
    FIG. 8 represents an embodiment of a device integrating a detector of supply disturbances, positive and / or negative.
    The device 801 comprises a voltage regulator 803 (REG) coupled between an application terminal of a supply potential 807 and a ground terminal 806 (GND). The controller 803 generates a supply voltage 805 (VDC) from a voltage applied to the power application terminal 807 (VBATT). The device further comprises a main circuit (MAIN FUNCTION) 804 and a supply disturbance detector 802 (DET), coupled between the supply voltage 805 and the ground 806. The disturbance detector 802 and the circuit 804 are connected. together.
    When a power disturbance attack is performed on the power application terminal 807, if this disturbance is large enough to be propagated through the regulator 803, it is found on the supply voltage 805. If the amplitude of the disturbance is above the detection threshold and above the disturbance frequency as defined in the embodiments of FIGS. 5 and 7, while the detector 802 detects a disturbance. Through the link between the detector 802 and the main circuit 804, then follows a sequence of spots, which can be sending a signal indicating the main circuit that an attack is in progress, the standby of the main circuit , or any other action.
    Figure 9 shows another embodiment of a device incorporating a supply disturbance detector.
    The device 901 comprises a voltage regulator 903 (REG) coupled between an application terminal of a supply potential 907 and a ground terminal 906. The regulator 903 generates a supply voltage 905 (VCC) from a voltage applied to the application terminal of the supply potential 907 (VBATT). The device further comprises a main circuit (MAIN FUNCTION) 904 coupled between the supply voltage 905 and the ground 906, as well as a disturbance detector (DET) coupled between the terminal for applying a supply potential. and the mass terminal. The disturbance detector 902 and the circuit 904 are connected together.
    The difference with respect to the embodiment described in FIG. 8 is that the supply disturbance detection is made directly at the power supply application terminal. Other embodiments of devices may combine the integration of different power disturbance detectors coupled to different internal supply voltages and / or different supply potential application terminals of said devices. Other variants of the embodiments described above are possible for detecting positive and / or negative power supply disturbances on devices coupled between an application terminal of a negative supply potential and a ground terminal, or between an application terminal of a positive supply potential and an application terminal of a negative supply potential.
    权利要求:
    Claims (12)
    [1" id="c-fr-0001]
    A circuit comprising, in series between a first terminal (508, 708) and a second terminal (509, 709) for applying a supply voltage (VCC): a first branch comprising a first transistor (501, 701) ) and a first current source (506, 706); a second branch comprising a resistive element (503, 703), a second transistor (502, 702) mounted in mirror with the first transistor and a second current source (507, 707), said resistive element conditioning a detection threshold of a variation of the supply voltage.
    [2" id="c-fr-0002]
    2. Circuit according to claim 1, comprising a low-pass filter connected to the gates of the transistors (501, 701, 502, 702) mounted in current mirror.
    [3" id="c-fr-0003]
    The circuit of claim 1, wherein a low-pass filter (704, 705) couples the first power supply terminal (708) and the resistive element (703).
    [4" id="c-fr-0004]
    The circuit of any one of claims 1 to 3, wherein said transistors (501, 701, 502, 702) are MOS transistors.
    [5" id="c-fr-0005]
    The circuit of any one of claims 1 to 3, wherein said transistors (501, 701, 502, 702) are bipolar transistors.
    [6" id="c-fr-0006]
    The circuit of any preceding claim, wherein said current sources (506, 507, 706, 707) are made with transistors.
    [7" id="c-fr-0007]
    The circuit of claim 6, wherein the ratio of the dimensions of the transistors constituting the current mirror (501, 701, 502, 702) and the ratio of the transistors constituting the current sources (506, 507, 706, 707) are different from 1.
    [8" id="c-fr-0008]
    The circuit of any preceding claim, wherein the resistance of the resistive element (503, 703) is programmable.
    [9" id="c-fr-0009]
    The circuit of any of the preceding claims, wherein the current sources (506, 507, 706, 707) are derived from a temperature-independent voltage reference and a resistor of the same type as the resistive element (503, 703) conditioning the detection threshold.
    [10" id="c-fr-0010]
    An apparatus comprising: a supply regulator (803, 903); a function (804, 904) powered by said regulator (804, 904); and a circuit (802, 902) according to any one of the preceding claims.
    [11" id="c-fr-0011]
    The device of claim 10, wherein said circuit (802) is powered by said regulator (803).
    [12" id="c-fr-0012]
    12. Device according to claim 10, wherein said circuit (902) is fed upstream of said regulator (903).
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    法律状态:
    2016-09-21| PLFP| Fee payment|Year of fee payment: 2 |
    2017-04-28| PLSC| Publication of the preliminary search report|Effective date: 20170428 |
    2017-09-21| PLFP| Fee payment|Year of fee payment: 3 |
    2018-09-19| PLFP| Fee payment|Year of fee payment: 4 |
    2019-09-19| PLFP| Fee payment|Year of fee payment: 5 |
    2021-07-09| ST| Notification of lapse|Effective date: 20210605 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1560259A|FR3042876B1|2015-10-27|2015-10-27|DETECTION OF DISTURBANCES OF A POWER SUPPLY|FR1560259A| FR3042876B1|2015-10-27|2015-10-27|DETECTION OF DISTURBANCES OF A POWER SUPPLY|
    US15/076,955| US10067200B2|2015-10-27|2016-03-22|Detection of disturbances of a power supply|
    US16/047,743| US10670666B2|2015-10-27|2018-07-27|Detection of disturbances of a power supply|
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